What is an array in solid state?

An array in solid state refers to a systematic arrangement of circuit elements on a single substrate in an integrated circuit (IC). It allows for the implementation of complex functions and large memory capacities in a small area. Some key aspects of arrays in solid state devices are:

Types of Arrays

There are several types of arrays used in solid state devices:

  • Memory arrays – Used to store data and program code. Examples are SRAM, DRAM, ROM arrays.
  • Logic arrays – Used to implement combinational and sequential logic functions. Examples are PLAs, PALs, FPGAs.
  • Sensor arrays – Used for imaging and other sensing applications. Examples are CMOS image sensors, ultrasonic transducer arrays.

Array Organization

The elements in an array are organized in rows and columns. For example, in a memory array, the rows correspond to wordlines and columns to bitlines. The intersection of a row and column identifies each element.


Key benefits provided by using arrays include:

  • High density – Many elements in small chip area leading to reduced cost.
  • Parallelism – Simultaneous access to multiple data bits.
  • Regular structure – Simplified layout and fabrication.
  • Modularity – Arrays can be easily scaled.

Memory Arrays

Memory arrays are fundamental building blocks used extensively in memory chips and microprocessors. They allow storage of binary data in a compact, efficient way. Let’s look at the structure and working of some common memory arrays.

SRAM Array

Each bit in an SRAM (Static RAM) array is stored in a bi-stable circuit called a bit cell or memory cell. A typical 6T SRAM cell uses 6 MOSFETs to implement a bistable latch for storing one bit. An SRAM array is organized as a matrix of bit cells with wordlines along rows and bitlines along columns. To read data from a cell, the wordline is asserted to connect the cell to the bitlines. The differential voltage on the bitlines is sensed by a sense amplifier which reads the stored value. Write operation also takes place in a similar way through the bitlines.

Figure 1: 6T SRAM bit cell and memory array organization

Some key features of SRAM arrays:

  • High speed – Fast access time in the order of a few nanoseconds.
  • Low power – No refresh required and negligible standby current.
  • Full CMOS – Robust storage using cross-coupled inverters.
  • High cost – Requires 6 transistors per bit so dense integration is limited.

SRAM is used for CPU cache memories and other applications requiring fast access.

DRAM Array

Unlike SRAM, DRAM (Dynamic RAM) stores each bit in a simple capacitor that needs periodic refresh. A 1T-1C DRAM cell uses just one access transistor and a capacitor to implement one bit storage. Due to this compact storage, DRAM arrays can achieve very high density. The array organization is similar to SRAM with rows as wordlines and columns as bitlines. The access transistor acts as a switch to control access to the storage capacitor during read/write operations. The stored voltage on the capacitor represents logic 1 or 0.

Figure 2: 1T-1C DRAM bit cell and memory array

Some key attributes of DRAM arrays are:

  • High density – Up to gigabits per chip possible.
  • Low cost per bit – Just 1 transistor and capacitor needed per bit.
  • Slower access – Typical access time around 50-70 ns.
  • Refresh required – Each bit needs periodic refresh every few ms.

DRAM provides inexpensive, high-density main memory for computers and other devices.

ROM Array

ROM (Read Only Memory) arrays are used to permanently store fixed data such as program code or lookup tables. A ROM cell is implemented using MOSFETs wired to represent a 1 or 0. Common ROM bit cells include:

  • Mask ROM – Coded during manufacturing using custom masks.
  • PROM – Programmable once using fuses or anti-fuses.
  • EPROM – Erasable using UV light and reprogrammable.
  • EEPROM – Electrically erasable and reprogrammable.

A ROM array is organized with wordlines and bitlines similar to RAM arrays. The stored data is fixed during manufacture or programming. During read, the ROM cells drive the bitline voltage to the sensed value. ROM arrays are compact and inexpensive but not reprogrammable.

Logic Arrays

Logic arrays consist of regular arrangements of uncommitted logic gates and switches. They can be configured by the user to implement custom logic functions without having to design a new chip. Some popular types are:

PLA (Programmable Logic Array)

A PLA contains an AND gate plane followed by an OR gate plane. The AND plane implements the product terms while the OR plane generates the logic function outputs by summing the product terms:

Figure 3: PLA structure

By selectively programming the connections in the AND and OR planes, desired logic functions can be implemented. PLAs are useful for random logic using a small number of inputs.

PAL (Programmable Array Logic)

PALs consist of a programmable AND array followed by fixed OR gates:

Figure 4: PAL structure

The AND array is customized to generate product terms, while the OR gates provide the logic outputs. PALs are more efficient than PLAs for implementing combined logic functions.

FPGA (Field Programmable Gate Array)

FPGAs contain an array of logic blocks interconnected by programmable routing. Logic blocks typically include flip-flops, LUTs, muxes and gates. Users can customize both the logic blocks and the routing to implement very complex logic functions. Modern FPGAs contain billions of gates and are used for ASIC prototyping, aerospace and defense systems, among other applications.

Figure 5: FPGA structure

In summary, logic arrays allow implementation of glue logic, control logic and complex functions using standard chips that can be customized as needed.

Sensor Arrays

Sensor arrays contain arranged sensor elements to enable imaging and spatially-resolved sensing. They take advantage of solid-state fabrication to integrate multiple sensing pixels in a compact area. Some examples include:

CMOS Image Sensors

CMOS image sensors consist of photodiode arrays fabricated in a CMOS process. The array detects light intensity and converts it into voltage/charge using the photoelectric effect in the photodiodes. Active transistors associated with each photodiode buffer and amplify the signals. CMOS sensors are widely used for camera imaging in mobile phones, cameras, scientific imaging etc.

Figure 6: CMOS image sensor array

Ultrasonic Transducer Arrays

These contain piezoelectric elements fabricated using materials like PZT. By exciting each element separately using electronic pulses, ultrasonic beamforming and steering can be performed. This enables advanced imaging techniques like 3D ultrasound. Transducer arrays are used in medical ultrasound, non-destructive evaluation etc.

Figure 7: Ultrasonic transducer array

MEMS Sensor Arrays

Using silicon micromachining, various MEMS sensors like accelerometers, gyroscopes and pressure sensors can be manufactured in arrays on a chip. Interface circuitry integrated on the same substrate provides amplification, conditioning and digitization. MEMS sensor arrays are finding applications in automation, vehicles, IoT devices and other fields.

Fabrication of Arrays

Solid-state arrays are fabricated on semiconductor substrates like silicon using techniques like:

  • Photolithography – To pattern transistors, metallization at microscopic scale.
  • Doping – To define n and p regions for transistors.
  • Etching – To remove materials and pattern layers.
  • Deposition – To deposit thin layers of materials like polysilicon, dielectrics.
  • CMP – For planarization and smoothing.

Repeated application of these processes allows building up of complex ICs like processors containing billions of transistors.

Fabrication Steps

A typical CMOS array fabrication sequence involves steps like:

  1. Start with a silicon substrate wafer
  2. Grow thermal oxide for insulation
  3. Deposit and pattern polysilicon gates
  4. Ion implantation to dope source/drain regions
  5. Deposit oxide and etch contacts
  6. Deposit and pattern metal interconnects
  7. Repeat steps to build multilayer structure
  8. Wafer testing and dicing

Advanced techniques like high-resolution lithography, 3D NAND stacking, backside illumination etc. are used for latest devices.

Table 1: Typical process steps for array fabrication
Step Purpose
Oxidation Grow insulating oxide layer
Lithography Pattern layers using imaging
Etching Selectively remove materials
Ion implantation Dope specific regions
Thin film deposition Deposit materials like polysilicon, metal
Planarization (CMP) Smooth layers

Design and Analysis

To implement arrays efficiently, extensive design and analysis is required:

  • Modeling – Mathematical modeling of devices, interconnects, circuits, timing, power etc.
  • Simulation – Usage of CAD tools like SPICE, Verilog, Ansys for design verification.
  • Physical design – Floorplanning, place and route, layout optimization.
  • Verification – Ensure logic, timing, power, reliability and other parameters are met.
  • Test – Exhaustive testing to screen defects and infant mortalities.

Highly calibrated process control and metrology is also needed to achieve required yields and performance.


Some challenges faced in array design today include:

  • Controlling leakage and power density as transistors scale down to 10nm and below.
  • Maintaining adequate signal-to-noise ratio and reliability for small node sizes.
  • Mitigating crosstalk and interference as interconnects get closer.
  • Managing heat dissipation from increasing power density.
  • Economically keeping pace with Moore’s law.

Innovations in architecture, materials, packaging and process technology are needed to address these.


Arrays are ubiquitous in modern solid-state electronics. Some major applications are:

  • Computers – Processor chips, cache memory, RAM and ROM.
  • Mobile – Application processors, cellular radio, CMOS image sensors.
  • Consumer – Display drivers, NAND flash, Bluetooth, WiFi.
  • Automotive – ADAS sensor arrays, infotainment systems.
  • IoT – Microcontrollers, MEMS sensor interfaces.
  • Aerospace/Defense – Avionics processors, phased array radars.
  • Medical – Implants, ultrasound and imaging systems.

The performance, functionality and efficiency of practically every modern electronic system relies on arrays implemented using solid-state integrated circuit technology.


To summarize, arrays organized as rows x columns are critical building blocks enabling the capabilities of integrated circuits. Implemented using solid-state fabrication, they provide the foundations for memory, logic, sensing and processing in devices all around us. Sophisticated design and precise manufacturing are needed to continuously advance array technology and fulfill Moore’s law. The next generation of smart systems across consumer, industrial, automotive and other sectors will be enabled by pushing the boundaries of solid-state arrays to new extremes.