SSDs, or solid state drives, are a type of computer storage device that uses flash memory to store data persistently. Unlike traditional hard disk drives (HDDs) which use spinning magnetic disks, SSDs have no moving parts and utilize integrated circuits to retain data.
How is data stored on a SSD?
Data is stored on a SSD in memory cells made up of floating gate transistors. Each memory cell can store one or more bits of data using two distinct voltage levels per cell, with the voltage levels representing binary 1s and 0s. Groups of memory cells are organized into pages, blocks, and planes. Data is written to and read from the SSD by manipulating the voltages of the cells.
Floating Gate Transistors
The floating gate transistor is the basic building block of SSD flash memory. It operates similarly to a normal field effect transistor, except that it has an extra “floating” gate suspended between the normal control gate and channel. The presence or lack of charge on the floating gate impacts the flow of current through the transistor channel, allowing it to store information.
Memory Cells
Individual floating gate transistors are incorporated into memory cells, the smallest unit of data storage on a SSD. A single memory cell stores one or more bits of data depending on the number of distinct voltage levels it can represent. For example, SLC flash uses 1 bit per cell, while MLC uses 2 bits per cell.
Pages, Blocks and Planes
Memory cells are organized into pages, blocks, and planes. A page is the smallest unit that can be written to or read from, typically 4-16kB in size. Pages are grouped into blocks, usually 128-256 pages per block. Blocks are in turn grouped into planes, with each plane operating semi-independently.
How is data organized on a SSD?
SSDs utilize a complex logical mapping scheme known as the Flash Translation Layer (FTL) to organize how data is physically stored on the drive. This allows the SSD to operate similarly to HDDs from the host system’s perspective.
Logical Block Addressing
Data on SSDs appears linearly addressed just like on HDDs, referred to as Logical Block Addressing (LBA). The host system reads and writes data as a sequence of logical blocks. The FTL translates the LBAs to physical block addresses (PBAs) where data is actually stored.
Flash Translation Layer
The Flash Translation Layer manages the process of mapping between logical and physical addresses. It is implemented as firmware on the SSD controller. Key jobs include:
- Read/write caching – improves performance
- Wear leveling – spreads writes across all cells evenly
- Bad block mapping – avoids using failed or unreliable cells
- Garbage collection – reclaims unused space
How is data written to a SSD?
Data is written to a SSD by applying different voltage levels to floating gate transistors to set their threshold voltage levels. This programs each cell to a data state representing one or more bits.
Erasing Cells
Before cells can be programmed, they must be erased, which resets them to a known baseline voltage level. Cells are erased in blocks rather than individually.
Programming Cells
To program cells, the FTL determines which physical location the data should be written to based on wear leveling algorithms and garbage collection. A high voltage is applied to raise the cell’s threshold voltage to the level representing the data being stored.
Buffering and Caching
For improved performance, data is first buffered in the SSD controller’s RAM. The FTL accumulates and organizes writes into full pages before programming.
How is data read from a SSD?
Data is read from a SSD by detecting the threshold voltage level of each floating gate cell. This provides a binary value that the controller maps back to the original data state of the cell.
Sensing the Cell Voltage
To read a cell, a specific voltage is applied to the control gate while monitoring the current flow through the cell channel. The amount of current indicates the cell’s voltage level, decoding it into a 1 or 0.
Error Checking and Correction
Because cell voltages can drift over time, error checking like CRC and ECC is used to detect and correct small errors in the read data. Retries and eventually marking cells as bad help handle larger issues.
Caching and Buffering
For performance, data reads are cached and buffered in the SSD controller memory. The FTL organizes small random reads into full page sequential reads to improve throughput.
How does an SSD controller work?
The SSD controller is the brains of the SSD, managing all interactions between the host system and the flash memory. It has the following key responsibilities:
- Host interface – Supports host interconnect protocols like SATA, PCIe, etc.
- Flash Interface – Manages the low level control of the flash memory.
- Processor – Runs firmware that implements the FTL and other logic.
- Memory – Provides caching and buffering for mappings, reads and writes.
By abstracting away the complexities of the underlying flash, the controller presents the SSD as a simple, high performance block device to the host system.
What is the process of garbage collection?
Garbage collection is the process of reclaiming unused pages on the SSD so that they can be reused for future writes. It is performed by the controller at the block level.
Why Garbage Collection is Needed
Because SSDs can only directly write empty cells, over time partially used blocks build up. Garbage collection consolidates data to free up these blocks for erasing and reuse.
Identifying Invalid Pages
The FTL identifies blocks with a high percentage of invalid pages using metadata like validity bits on each page. This signals blocks that are good candidates for garbage collection.
Relocating Valid Data
Any remaining valid data in the identified blocks is read, then re-written to a new block. The original block is then erased to be ready for reuse.
Scheduling Garbage Collection
Garbage collection is scheduled intelligently so it does not compete with host requests. It may run in the background when the host is idle, or briefly pause host operations.
What is wear leveling and how does it work?
Wear leveling refers to the process of evenly distributing writes across the blocks of the SSD over time. This avoids prematurely wearing out frequently written blocks.
Why Wear Leveling is Needed
NAND flash can only sustain a finite number of erase cycles before wearing out. If the same blocks were reused, they would wear out quickly.
Static vs Dynamic Wear Leveling
In static wear leveling, data is written sequentially across blocks to spread writes. Dynamic wear leveling additionally rebalances existing data across blocks.
Wear Leveling Algorithms
Simple schemes fill blocks one after the other evenly. More advanced algorithms move data from highly worn blocks to evenly distribute wear over time.
Indicating Block Wear
The controller tracks how many erase cycles each block goes through, known as the erase count. This data guides wear leveling algorithms.
How is bad block management handled on SSDs?
Bad block management refers to the process of detecting blocks of NAND flash that are faulty or unreliable and marking them as bad to prevent their use.
Causes of Bad Blocks
Bad blocks occur due to issues like manufacturing defects, read/write disturbances, or blocks wearing out from excessive erase cycles.
Detecting Bad Blocks
SSD controllers run diagnostic tests to identify bad blocks, and also detect them during normal operation when repeated read/write failures occur.
Bad Block Mapping
The FTL maintains a bad block table in RAM, storing bad block markers to prevent their use. The table maps bad blocks to spare good blocks as replacements.
Impact of Bad Blocks
A small number of bad blocks has minimal impact, as the FTL simply avoids accessing those specific blocks. But excessive bad blocks can significantly reduce usable SSD capacity.
How does TRIM help maintain SSD performance?
The TRIM command improves sustained write performance by letting the SSD know which blocks of deleted data can be wiped and reused immediately.
Write Performance Slowdown
Without TRIM, deleting files simply marks data as invalid. Until garbage collection wipes blocks, their performance declines.
TRIM Operation
TRIM allows the OS to notify the SSD which blocks contain invalid pages. The SSD can then prioritize erasing these blocks.
Benefits of TRIM
With TRIM, unused pages get wiped promptly, improving steady state performance. TRIM also reduces fragmentation and the need for resource-intensive garbage collection.
What is DRAM cache and how does it benefit SSDs?
DRAM cache refers to a small amount of fast DRAM memory integrated directly onto the SSD controller to assist with managing data flow. Key benefits include:
- Caching mapping table – Avoid flash lookups for logical to physical translations.
- Read/write buffering – Improve throughput and latency.
- Streaming writes – Combine small random writes into full page writes.
- Reduced wear – Absorb redundant writes that would go to flash.
For write-heavy workloads, DRAM cache improves performance, endurance, and lifespan of SSDs.
What are the main differences between SLC, MLC and TLC NAND flash?
| Metric | SLC | MLC | TLC |
|---|---|---|---|
| Bits per cell | 1 | 2 | 3 |
| Number of voltage levels | 2 | 4 | 8 |
| Density | Low | Medium | High |
| Performance | High | Medium | Low |
| Endurance | High | Medium | Low |
| Cost | High | Medium | Low |
In general, SLC provides the highest performance and endurance while TLC provides the lowest. But TLC allows fitting more data into lower cost flash.
What is 3D NAND and how is it different from planar NAND?
3D NAND is a flash memory technology that stacks memory cells vertically in three dimensions. This contrasts with conventional planar NAND that arranges cells in a flat two-dimensional array.
Higher Density
By stacking cells vertically, 3D NAND achieves much higher densities in a smaller footprint. More layers and bits per cell increase density further.
Lower Cost Per Bit
The compact structure of 3D NAND reduces the cost per bit compared to planar NAND. Vertical connections eliminate the need for much circuitry.
Better Performance
Smaller parallel communication paths enable lower latency and power consumption. The compact structure also allows more dies per package for parallelism.
Higher Reliability
With data programmed in pages, 3D NAND is less vulnerable to individual cell errors and single layer failures. Endurance also improves.
What is QLC NAND and how does it compare to TLC NAND?
QLC (quad-level cell) NAND is a newer NAND technology that stores 4 bits of data per cell, allowing higher densities than TLC NAND.
Higher Density
With 16 distinct voltage levels per cell, QLC provides 33% greater density than TLC NAND flash.
Lower Performance
Having more voltage levels makes QLC slower than TLC, with reduced data transfer speeds and interface bandwidth.
Lower Endurance
With more voltage states per cell, QLC endurance is reduced compared to TLC. Lifespan ratings are typically around 500-1000 erase cycles.
Lower Cost
Despite drawbacks, QLC is significantly cheaper per GB compared to TLC. This makes it viable for read-centric consumer workloads.
Ideal Workloads
QLC is best suited for sequential data writes like media storage, backups, surveillance footage, etc. rather than heavily random workloads.
Conclusion
SSDs provide persistent, high-speed storage for computers and other devices using NAND flash memory cells. Careful engineering of the flash translation layer software enables SSDs to emulate block storage and optimize performance through techniques like caching, wear leveling, and garbage collection. Continued evolution of flash with advances like 3D stacking enables SSDs to offer ever higher capacities at lower costs.
